Integrated circuit memory devices such as synchronous dynamic random access memory devices (SDRAMs) have thousands of memory cells. Each memory cell is capable of storing data in the form of an electric charge. In order to read the data in a particular memory cell, the memory cell is selectively coupled to a sense circuit via a communication line, commonly referred to as a digit line. Typically, the sense circuit is connected to a pair of digit lines and detects a voltage differential between the digit lines caused by the stored charge. Prior to coupling a memory cell to a digit line, the pair of digit lines are equilibrated to a predetermined voltage level. After the sense circuit amplifies the voltage differential on the pair of digit lines, the digit lines are coupled to data input/output (I/O) communication lines for data communication with external devices. In order to accelerate the read operation, and to minimize operational power consumption, the I/O lines of the SDRAM are typically equilibrated and precharged to an initial predetermined voltage, such as one half a supply voltage (Vcc/2). This allows the I/O lines to quickly develop a differential voltage when coupled to the amplified digit lines.
The internal operations of an SDRAM, including equilibrating the I/O lines, are tightly synchronized by an externally provided clock signal. For example, the I/O lines are typically equilibrated at a precise time during a memory access cycle. Therefore, the access time of the SDRAM is directly affected by the time at which the I/O lines are equilibrated during the access. In order to reduce the access time, there is a need in the art for a synchronous memory device which initiates the equilibration of the I/O lines as early in the access cycle as possible. More specifically, there is a need in the art for a memory device that, when possible, decouples the timing of the equilibration operation from the clock signal and effectively asynchronously initiates the equilibration of the I/O lines.